1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device having an MPU (Micro Processing Unit) and a DRAM (Dynamic Random Access Memory) as a secondary cache mounted on a chip wherein it is possible to prevent a data transmission delay during normal operation from increasing caused by a test writing for a DRAM part.
2. Description of the Related Art
As to a chip on which an MPU and DRAM as a secondary cache are mounted, when an evaluation test is tried for only the DRAM part, it is generally difficult to carry out the test for the DRAM part via the MPU, namely, using the function of the MPU.
Therefore, it is necessary to execute the test using a memory tester or the like after taking all data in the data buses between the MPU and the DRAM out to the outside via a test pad.
FIG. 7 is a block diagram explaining a conventional test procedure for a DRAM part in a chip on which an MPU and a DRAM as a secondary cache are mounted.
An MPU 101 and a DRAM part 102 are connected by data buses 104 via an output/input buffer (OUT/IN) 103. In this case, for example, when 138 buses are used for the secondary cache and 33 buses are used for a TAG memory storing with tags showing data stored in the secondary cache, the total of the data buses 104 is 171.
In order to make the test for the DRAM part possible, it is necessary to previously construct the chip in a manner that all of the data buses connected to the DRAM part are connected in parallel to a test bonding pad 106 via a test wiring 105 and are connected to a memory tester (not shown), and thereby a test is carried out.
However, in the chip on which the MPU and the secondary cache are mounted, as shown in FIG. 7, when all of the data buses between the MPU and the DRAM part are connected to the pad, large parasitic capacitance is added to the data buses between the MPU and the DRAM part caused by the test wiring or the like, there is a problem in that a delay of data transmission between the MPU and the DRAM increases.
Further, there is another problem in that areas shared for pads on the chip increase as the number of pads increases compared with a chip having only an MPU.
In view of the above difficulties, it is an object of the present invention to provide a semiconductor memory device having an MPU and a DRAM as a secondary cache on one chip wherein it is possible to prevent a data transmission delay in normal operation caused by a test wiring of the DRAM part from increasing and it is possible to reduce the number of test pads.
According to a first aspect of the present invention, there is provided a semiconductor memory device in which a processing unit and a memory as a secondary cache are mounted on a chip, the semiconductor memory device comprising:
a plurality of data buses connecting the processing unit and the memory as the secondary cache;
a plurality of test data buses, each of the test data buses connected in parallel to each of the plurality of data buses;
registers for holding data temporarily; and
an external test terminal connected to the plurality of test data buses through the registers.
In the foregoing, a preferable mode is one wherein the external test terminal is a part of an external terminal for the processing unit.
Also, a preferable mode is one further comprising a switch for connecting the external test terminal with the registers or the plurality of data buses for the processing unit alternately.
Also, a preferable mode is one wherein a data transmission direction in the registers is changed depending on whether a test apparatus reads data from or writes data to the memory as the secondary cache.
According to a second aspect of the present invention, there is provided a semiconductor memory device in which a processing unit and a memory as a secondary cache are mounted on a chip; the semiconductor memory device comprising:
a plurality of data bus groups of data buses for connecting the processing unit and the memory as the secondary cache;
a plurality of test data bus groups of test data buses, each of the test data bus groups connected in parallel to each of the data bus groups;
selectors for selecting one test data bus group among the plurality of test data bus groups and respectively provided for the test data bus groups;
a multiplexer provided between a plurality of data buses in the selected test data bus group and an external test terminal and holding data of the plurality of data buses temporarily.
In the foregoing, a preferable mode is one wherein the external test terminal is a part of an external terminal of the processing unit.
Also, a preferable mode is one further comprising:
a switch for connecting the external test terminal with the multiplexer or the plurality of data buses for the processing unit alternately.
Also, a preferable mode is one wherein the selectors include a plurality of steps, and puts the plurality of test data bus groups together step by step so as to select one test data bus group.
Also, a preferable mode is one wherein a data transmission direction in the selectors is changed depending on whether a test apparatus reads data from or writes data to the memory as the secondary cache.
Also, a preferable mode is one wherein a data transmission direction in the multiplexer is changed depending on whether a test apparatus reads data from or writes data to the memory as the secondary cache.
According to the present invention, in the semiconductor memory device in which a processing unit and a memory as a secondary cache are mounted on a chip and are connected with a plurality of data buses, a plurality of test data buses connected in parallel to the plurality of data buses are connected to an external test terminal via registers for holding data temporarily, therefore, the capacitance added to the data buses between the processing unit and the secondary memory becomes small. As a result, it is possible to prevent the data transmission delay between the processing unit and the secondary memory in the normal operation from increasing. Also, it is possible to carry out the evaluation test for the memory as the secondary cache at a clock frequency equal to that of the actual operation.
Further, in this case, the external test terminal is a part of the external terminal for the processing unit, and is connected to the registers or the plurality of data buses alternately with the switches, therefore, it is impossible to prevent the number of terminals required for the unit test of the memory as the secondary cache from increasing.
Also, according to the present invention, in the semiconductor memory device in which a processing unit and a memory as a secondary cache are mounted on a chip and are connected with a plurality of data buses, the plurality of data buses between the processing unit and the secondary memory are divided into a plurality of groups, the selector selects one group among a plurality of groups of test data buses connected in parallel to the plurality of data bus groups, and the test external terminal is connected to the selected test data bus group via the multiplexer, therefore, the capacitance added to the data bus between the processing unit and the memory as the secondary cache becomes small. As a result, it is possible to prevent the data transmission delay between the processing unit and the secondary memory in the normal operation from increasing. Also, it is possible to carry out the evaluation test for only the memory as the secondary cache at a clock frequency equal to that of the normal operation. Moreover, it is possible to prevent the number of terminals required for the unit test of the secondary memory from increasing.
Further, in this case, the external test terminal is a part of the external terminal for the processing unit, and is connected to the multiplexer or the plurality of data buses alternately with the switches, therefore, it is possible to prevent the number of terminals required for the unit test of the memory as the secondary cache from increasing.